Semiconductor device and method of manufacturing a semiconductor device

ABSTRACT

A semiconductor device has a substrate having a plurality of neighboring trenches, and a contact area, one mesa stripe each being formed between two neighboring trenches. The contact area contacts mesa stripes and surrounds an opening region in which the contact area is not formed and which is formed such that the contact area contacts the same mesa stripes at two positions between which the opening region is arranged, and the opening region having a region of elongate extension which intersects the mesa stripes in a skewed or perpendicular manner.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Utility Patent Application claims priority from German PatentApplication No. 102007020249.2, which was filed on Apr. 30, 2007, and isincorporated herein by reference in its entirety.

TECHNICAL FIELD

Embodiments relate to a semiconductor device and to a method ofmanufacturing a semiconductor device and, in one embodiment, to skewedembedding of sensor structures.

BACKGROUND

There is often demand for providing efficient overload protection insemiconductor devices, like for example power field-effect transistors.This may, for example, be done by embedding a sensor structure whichexemplarily detects a sensor current, wherein this sensor current isproportional to a current through the power field-effect transistor, ina field of cells of a power field-effect transistor. When the sensorstructure is embedded in a field of cells of the power field-effecttransistor such that the leads are perpendicular (or parallel) to one ofthe sides of the field of cells/chip and/or the direction of trenchstripes, the result may be semi-floating potential (body) regions alongthe leads. The semi-floating potential regions may, depending on theembedding depth of the sensor structure, be considerably longer than 200μm or even be in the range of mm. Semi-floating potential regions aretaken as regions which are geometrically long but not formed as an area,but only connected to a defined potential at the ends. With fast voltagepulses having very steep edges (like for example ISO pulses or ESD(electrostatic discharge) events), the result may be that the potentialalong such a semi-floating region and/or semi-floating potential regionis dynamically strongly different. Close to contact points, thepotential will follow the set value very quickly, however at theremotest position, it may still dynamically exhibit an unfavorablepotential value such that gate oxide stress or even voltage breakdownsand damage may occur in neighboring trenches. Reliability risks and, inthe worst case, local destruction of the power transistor are theresults.

Embodiments thus deal with the field of optimum embedding of sensorstructures in a large-area field of cells of a power transistor.

For these and other reasons, there is a need for the present invention.

SUMMARY

One embodiment provides a semiconductor device including a substratehaving a plurality of neighboring trenches, and a contact area, one mesastripe each being formed between two neighboring trenches. The contactarea contacts the mesa stripes and surrounds an opening region in whichno contact area is formed and which is shaped such that the contact areacontacts the same mesa stripes at two positions between which theopening region is arranged, the opening region including an elongateextension region intersecting the mesa stripes in a skewed orperpendicular manner.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the present invention and are incorporated in andconstitute a part of this specification. The drawings illustrate theembodiments of the present invention and together with the descriptionserve to explain the principles of the invention. Other embodiments ofthe present invention and many of the intended advantages of the presentinvention will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

Embodiments will be detailed subsequently referring to the appendeddrawings.

FIG. 1 is a schematic illustration of an opening region of a contactarea for a semiconductor device according to an embodiment.

FIGS. 2 a to 2 c show schematic illustrations of an embedded sensorstructure in the semiconductor device having semi-floating potentialregions according to embodiments.

FIG. 3 is a schematic illustration of a conventional embedding of asemiconductor structure in the semiconductor device having semi-floatingpotential regions.

FIG. 4 illustrates a schematic layout view of an embedding of afield-effect transistor in the field of cells of a power field-effecttransistor.

FIG. 5 is an enlarged illustration of a section of a cross-sectionalillustration of FIG. 4 along the intersection line 2-2′.

FIG. 6 is a schematic cross-sectional illustration through the powerfield-effect transistor of FIG. 4 along the intersection line 3-3′.

FIG. 7 illustrates a schematic sectional view through a mesa of FIG. 4along the intersection line 6-6′.

FIG. 8 illustrates a circuit diagram of an integrated power transistorthe load transistor and sensor transistor of which are each realized asN-DMOS transistors.

Before embodiments will be discussed in greater detail referring to thedrawings, it is pointed out that, in the figures, same elements orelements having the same effect are provided with same or similarreference numerals, and that a repeated description of these elements isomitted.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purposes ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope. The following detaileddescription, therefore, is not to be taken in a limiting sense, and thescope is defined by the appended claims.

Embodiments relate to a semiconductor device, for example a powertransistor or a power field-effect transistor, including a substratewhich includes a plurality of neighboring trenches and in which a mesastripe is formed between two respective neighboring trenches. A contactarea contacting the mesa stripes is formed for contacting thesemiconductor device, the contact area leaving out an opening region sothat there will be no contacting of the mesa stripes by the contactregion in the opening region. The opening region here is implementedsuch that the contact area contacts mesa stripes at two separatepositions and that the opening region is located between the twoseparate positions. In addition, the opening region has an elongateextension and intersects the mesa stripes in a skewed or perpendicularmanner. Specific embodiments of the opening region will be discussed ingreater detail below.

The opening region within the semiconductor device may, for example,serve to embed another device, like for example a sensor structure, inthe semiconductor device. Embodiments are based on the idea ofoptimizing macroscopic embedding of an exemplarily sensor and/or sensorstructure. Macroscopic embedding here is taken as a geometrical shape ofhow the sensor structure of a device can be embedded in the field ofcells of the neighboring trenches. It deals with optimum embedding ofthe sensor structure or a current sensor in the field of cells in thesense of the most homogeneous embedding possible on the microscopiclevel. Homogeneous embedding here exemplarily relates to the trenchgeometry, the potential regions which, in the course from the field ofcells into the current sensor, should be as uniform as possible.

The neighboring trenches may exemplarily be arranged on a substratesurface and when the device exemplarily is a power field-effecttransistor, the substrate side opposite the surface may exemplarilyinclude a drain electrode (or drain) or drain region and source regionsare formed along the mesa stripes. The source regions may exemplarily beformed by correspondingly doped regions within the mesa stripes and arecontacted by the contact area. Body regions may exemplarily be formedbetween the source regions and the drain region. The source regions andthe drain region usually exhibit equal doping of the semiconductorsubstrate and the body regions exhibit a corresponding complementarydoping. Gate regions of the exemplarily power field-effect transistormay be formed within the trenches and are separated from the substrateand the contact area by an insulation. The insulation of the gateregions and body regions here is located such that when applying acorresponding voltage (the sign of which depends on the doping selected)to the gate regions, channels will form along a trench wall in the bodyregions so that a current can flow from the source regions to the drainregion. Optionally, a higher doped layer may be deposited in the drainregion and be contacted electrically to a drain electrode in order toimprove a drain terminal.

Embedding the exemplary sensor structure in the power field-effecttransistor just described may take place such that the contacting(contact area) is opened along the source regions in an opening regionand the sensor structure is embedded in this opening region. Since thesource regions and the body regions are no longer contacted within theopening region, the semi-floating potential regions mentioned mayresult. This will particularly be the case if, as is the casefrequently, the body regions are through-contacted to the contact area.The through-contactings may, for example, be made by additionaltrenches, the consequence being that the body regions are connected toan equal potential as the source regions.

A simulation of potential error cases which may occur due tosemi-floating potential regions has the summarizing result thatsemi-floating potential regions of a length of less than 100 μm aregenerally uncritical; this is what makes embedding allowingsemi-floating regions of considerably less than 100 μm desirable. Likeembodiments illustrate, this is possible when embedding is performed ina skewed manner. In contrast to skewed embedding, semi-floatingpotential regions over a length corresponding to an embedding depth ofthe structure embedded will result when using a type of embedding wherethe lead is parallel to the neighboring trenches. However, when skewedembedding is performed and a lead to the device embedded is skewedrelative to the neighboring trenches, a considerable reduction in thelength of semi-floating regions can be achieved in dependence on theangle in which the lead intersects the neighboring trenches. In thiscase, the respective semi-floating potential regions can be contactedfrom both sides, which is not possible with straight embedding. Withskewed embedding, first of all, semi-floating regions will becomeconsiderably shorter and, secondly, be independent of the absolute valueof the overall embedding depth of the sensor and/or device and, thirdly,active cells at the potential of which they can be contacted are presenton both sides. If the intersection angle of the skewed embeddingrelative to neighboring trenches is selected to be sufficiently great(further details will follow), the result will be the two-sidedcontacting described before. These three characteristics result in areduction in the semi-floating potential region to a length ofconsiderably less than 100 μm. Dynamically semi-floating potentialregions for fast voltage pulses for example may be eased by embeddingsensor structures in the field of cells of a power transistor as justdescribed.

Generally, it will be of advantage to place the embedded structure asdeep as possible into the power field-effect transistor. This willparticularly be the case if the semiconductor structure embedded is asensor which is to experience most equal physical conditions possible(like for example potential structure, temperature etc.) and thus has acharacteristic curve which should, as far as possible, match that of thepower field-effect transistor. When the contact area is arranged in anXV plane, it will be of advantage for skewed embedding to select theopening region such that a maximum difference of the X coordinates ofthe opening region and a maximum difference of the Y coordinates of theopening region be, if possible, of the same order of magnitude. Thiswill exemplarily be the case if one of the following relations applies:⅙<ΔY/ΔX<6 or ½<ΔY/ΔX<3 or if ΔY matches ΔX up to a precision of 20%.Furthermore, it will be of advantage for the lead to the embedded sensorstructure to be dimensioned such that, on the one hand, the sensorstructure can be supplied with a sufficient amount of current, however,on the other hand, that the respective opening region in which the leadis located is kept as small as possible. This allows minimizinginterferences of the power field-effect transistor by the sensorembedded in the best way possible.

The resulting elongate extension of the opening region may be describedmathematically as follows. The opening region which is limited on theone hand by the contact area and, on the other hand, extends to a baseline, the base line representing an edge of the contact area, has anarea A and the edge of the opening region has a perimeter U. Usingthese, two geometrical quantities can be defined, namely, on the onehand, a first geometrical measure V₁=U/4 and, on the other hand, asecond geometrical measure which is defined by V₂=A/V₁. A definition foran elongate extension here can be made as follows. The following appliesfor the first length V₁ and the second length V₂: V₁=λV₂, λ>1. Thisrelation applies for every rectangular shape of the opening region incase the length of one side of the rectangle is longer than the lengthof another side (V₁ and V₂, however, are not the lengths of the sides ofa rectangle). The following would apply for a square: λ=1, and, for acircle, λ=U²/(16 A)=π/4<1. In case λ>4, with a rectangular shape of theopening region, the length of one side would be at least 10 timesgreater than the other side.

In case the contact area has a rectangular shape, in furtherembodiments, the opening region spreads to a corner of the contact area,the corners being determined by maximum/minimum X,Y values for thecontact area. In addition, the opening region may include a skewed partand a rectilinear part, wherein the skewed part may be characterized bythe edge of the opening region intersecting the neighboring trenches ina certain angle, and the straight part may be characterized by the edgeof the opening region being in parallel to a trench. The skewed portionof the opening region here may also be of a stepped shape, i.e., theedge of the opening region is either perpendicular or parallel to thetrenches, wherein it is of advantage in this case for the step heightand step width to be of the same order of magnitude and/or differ fromeach other by maximally 50%, or for the region which is perpendicular tothe neighboring trenches to be longer than the region which is parallelto the neighboring trenches. With a stepped design of the openingregion, however, it must be kept in mind that the region which isparallel to neighboring trenches be, exemplarily, of a length of at most200 μm or at most 100 μm in order to avoid the error cases describedbefore in semi-floating potential regions.

In further embodiments, the following relation applies for the angleand/or angle of inclination of a stepped design of the opening region:tan α=n/m, n being an integer multiple of a pitch distance in the Xdirection and M being an integer multiple of a pitch distance in the Ydirection. A pitch distance in the X direction exemplarily matches adistance between two through-contactings to the body regions. On theother hand, the pitch distance in the Y direction may exemplarily bedetermined by a distance (and/or mean value) between two neighboringmesa stripes.

In further embodiments, the embedded sensor structure also includesanother field-effect transistor which includes other source regions, andthe other source regions exemplarily also include doped regions alongthe further mesa stripes. Furthermore, the other field-effect transistorincludes other body regions, the other body regions being formed betweenthe other source regions and drain region. The drain region of the powerfield-effect transistor may exemplarily match the drain region of theembedded field-effect transistor, which means that the two regions arefor example at the same potential. In addition, the embeddedfield-effect transistor includes another gate region, the other gateregion also being in electrical contact to the gate region of the powerfield-effect transistor so that, here too, the corresponding gateterminal (or control terminal) is at the same potential as the gateterminal of the power field-effect transistor. As has been described forthe power field-effect transistor, when applying a corresponding voltageto the other gate region, channel regions form along a wall region ofthe trenches along which the embedded field-effect transistor is formed.These other channel regions allow a current to flow between the othersource region and the drain region. Since for the embedded field-effecttransistor, too, the further body regions are generally contacted by theother source regions, it is important for the other body regions to beelectrically insulated from the body regions of the power field-effecttransistor. This may be done by separating the body regions and theother body regions and by not forming body regions in a separationregion. However, the consequence is that a thick oxide in the trench isof advantage in the region with no body. In the thick oxide trenchesformed in this way, there are no source regions, i.e., the substrateextends to the surface and thus the drain potential is applied to theseregions. When the oxide layer which separates the other gate regionsfrom the trench wall is formed to a particular degree in the region ofthe thick oxide trenches, as has been mentioned, no electrical breakdownand/or damage to the oxide layer will occur due to the generally highpotential difference between the drain region and the gate region. Thefact that there are no body regions in the region of the thick oxidetrenches prevents current from flowing and/or potential adaptationbetween the body regions and the other body region and also, due to thethrough-contacting of the body regions with the source regions, a shortand/or an electrical current from flowing between the source regions andthe other source region.

Embodiments thus are of advantage in that the semi-floating potentialregions can be limited to a length which does not result in the deviceto be damaged. This is an advantage for fast switching devices wherepower field-effect transistors are frequently used and can increase boththe reliability and lifetime thereof significantly. It is also to bementioned that the design of the opening region does not necessarilyrelate to embedding a field-effect transistor or a sensor structure intoa power field-effect transistor, but may also be applied whereversemi-floating regions in the sense described before occur.

Before the individual figures will be described subsequently, it ispointed out here that these illustrations are not to scale. Inparticular, no conclusions with regard to vertical dimensions can bedrawn from the drawings with the embodiments of the terminal structures,nor can, with regard to lateral dimensions of the correspondingstructures, conclusions be drawn as to specific dimensionings ofimplementations of the embodiments. The imaging ratios chosen in thefigures are rather set with regard to clear representation anddiscussion of the embodiments. In the same way, no conclusions withregard to characteristic lengths of lateral structures may be drawn fromthe figures and especially small structures are frequently illustratedin an enlarged manner in order to describe the embodiments.

FIG. 1 is a schematic illustration of a design of an opening region 120of a contact layer M1 for a semiconductor device formed in substrate 110with a contact area M1. The semiconductor device is formed in asubstrate 110 including a plurality of neighboring trenches t₁, t₂, t₃,. . . . The substrate 110 may include other trenches which, however,cannot be seen in FIG. 1. A mesa stripe m₁ is located between twoneighboring trenches, like for example between the trenches t₁ and t₂,and a mesa stripe m₂ is located between the trench t₂ and theneighboring trench t₃. This arrangement is continued over an entirefield of cells, the field of cells including the entire semiconductordevice. The semiconductor device is contacted via the contact area M1which may exemplarily include a metal layer and also contact the mesastripe m_(i) (i=1, 2, 3, . . . ). In the embodiment illustrated here,the contact area M1 has a rectangular shape, i.e., it extends in an xyplane, which here is selected to be parallel to the contact area M1,from a value x=0 to a value x=x₁ and from a minimum Y value y=y₁ up to amaximum Y value y=y₂. Additionally, the contact area M1 includes anopening region 120, the opening region 120 extending from a base line130 which coincides with an edge of the contact area M1 (for which x=0),at first along a skewed subregion 120 a and then along a straightsubregion 120 b. The straight subregion 120 b is characterized in thatthe edge, in the X direction of the straight subregion 120 b, isparallel to one of the neighboring trenches t_(i), and the skewedsubregion 120 a is characterized in that the edge of the skewedsubregion 120 a encloses an angle α relative to the neighboring trenchest_(i).

The opening region 120 includes points in the xy plane the X values ofwhich include an X region Δx and the Y values of which include a Yregion Δy. Thus, two points of the opening region 120 in maximumdistance to each other exemplarily differ in the Y coordinate by Δy andin the X coordinate by Δx. The skewed portion of the opening region 120a which correspondingly extends in a Δxa region and a Δya regionexemplarily is implemented such that the ratio Δxa to Δya is between 0.1and 20 or between 0.5 and 3. In the embodiment of FIG. 1, Δya=Δy, inanother embodiment where the opening region has a skewed design (see,for example, FIGS. 2 b and 2 c) the two regions may differ.Alternatively, the skewed portion 120 a of the opening region 120 isselected such that the angle α is between 30° and 60°. Although in FIG.1 the skewed portion 120 a has a rectilinear edge to the contact areaM1, the edge may also have a stepped design, wherein in this case theangle α is defined such that it describes the angle between neighboringtrenches t_(i) and a straight, the straight corresponding to a meanincrease of subsequent processes in the X direction.

In order to achieve two-side contacting, the angle α should be selectedto be sufficiently great. This means that α>α_(min) applies, the minimumangle α_(min) corresponding to the case where just one trench iscontacted on both sides of the skewed portion 120 a. In this case, thefollowing relation applies: sin α_(min)=b/d, b being the mean width ofthe opening region 120 a and d indicating the embedding depth. In orderfor the opening region 120 a to intersect as many trenches as possible,however, a should be considerably greater than α_(min), exemplarilygreater by a factor of 5. The condition that semi-floating regions beuncritical, described before, for the angle α means that the followingrelation applies: 90≧α>arcsin (b/d_(crit)), d_(crit) being the criticallength of semi-floating potential regions (exemplarily d_(crit)=100 μm).

It is also to be pointed out here that the angle α generally is notselected to be continuous, but may exemplarily only be altered indiscrete processes. The discrete processes here are determined by thefact that when designing the opening region 120 it is of advantage forthe contact area M1 only to be opened at certain positions. Thesecertain positions may for example be the corresponding pitch distances,a pitch distance in the Y direction being determined by a mean distanceof two neighboring trenches and a pitch distance in the X directionbeing exemplarily determined by a mean distance of two neighboring bodythrough-contactings. The body through-contactings will be discussed ingreater detail below, wherein it is only to be pointed out here that thebody through-contactings may exemplarily be made at discrete positionson mesa stripes m_(i) along the X direction. The pitch distances in theX and Y directions may exemplarily be in a range of 1 to 4 μm or roughly2.75 μm.

FIG. 2 a illustrates an example of how a device may be embedded in theopening region 120. The contact area M1 extending along the xy plane andbeing limited along the X direction by the base line 130 is illustratedagain, the base line 130 corresponding to a maximum X value of thecontact area M1. The contact area M1 in turn has an opening region 120which is divided into a skewed opening region 120 a and a straightopening region 120 b, the straight opening region including a boundaryline 122 which is parallel to a mesa stripe m_(i) and intersects at mostfive mesa stripes m_(i). In addition to the embodiment illustrated inFIG. 1, the opening region 120 in FIG. 2 a has another straight openingregion 120 c, the other straight opening region 120 c extending betweenthe skewed opening region 120 a and the base line 130. Another contactarea M2 is formed within the opening region, the other contact area M2extending from the base line 130 into the opening region 120. Thestraight opening region 120 b has an embedded device which in theembodiment illustrated here is a transistor T_(s). The embeddedtransistor T_(s) is contacted electrically by a lead 140, the lead 140extending along the opening region 120 from the embedded transistorT_(s) to the base line 130. The contact area M1 and the other contactarea M2 are electrically insulated, wherein in the embodiment of FIG. 2a an insulating intermediate region 145 is arranged in the gap betweenthe contact area M1 and the other contact area M2.

As will be illustrated in greater detail below, the insulatingintermediate region 145 may be implemented as an oxide layer and extendpartly between the metal layer M1 and the substrate 110 and also partlybetween the other contact area M2 and the substrate 110. The result inthe transition region thus are a first and second intermediate regionsM1′ and M2′ where the contact areas M1 and M2 are separated from thesubstrate 110 by the insulating intermediate region 145. If theinsulating intermediate region 145 is not implemented as a layer, theregions M1′ and M2′ will be part of the contact areas M1 and M2. Sincethe embedded transistor T_(s) can also use the trench structure which inthis level of drawing is below same (not illustrated in the figure), itis necessary for the corresponding body regions of the embeddedtransistor T_(s) to be electrically insulated. Like described before,this may exemplarily be done by not forming body regions in anintermediate region, wherein it may be of advantage in this intermediateregion to form a thick oxide layer in the trench (thick oxide layersD_(t)). Before discussing a specific realization of the embeddedtransistor T_(s) in a field of cells of a power transistor in thefollowing figures, the semi-floating potential regions F are first to becharacterized in greater detail.

The semi-floating potential regions F can be divided into shortsemi-floating potential regions F1 and long semi-floating potentialregions F2 and are illustrated in FIG. 2 a by perpendicular thin lines.The semi-floating potential regions F extend to regions where the mesastripes m_(i) are not contacted by the contact area M1. This is, forexample, the case in the opening region 120 and/or when the insulatingintermediate region 145 is formed between the contact area M1 and thesubstrate 110. Depending on the geometry of the opening region 120, thesemi-floating potential regions F may include different lengths. Theshort semi-floating potential regions F1 will result along the skewedopening region 120 a and the long semi-floating potential regions F2along the straight opening region 120 b and extend partly along theskewed opening region 120 a. Both semi-floating potential regions F1 andF2 in this embodiment are contacted from both sides by the contact areaM1 which performs potential equalization at this position. Thesemi-floating potential regions F may exemplarily include body regionsor source regions of the underlying trench structure (see below).

In addition to the semi-floating potential regions F which are contactedfrom both sides, there may be potential regions which are contactedelectrically by the contact area M1 only on one side. However, in oneembodiment, these additional semi-floating potential regions F3 areshorter than the long semi-floating potential regions F2. With greatoverall embedding depths of the exemplarily embedded transistor T_(s),the short semi-floating potential regions F1 may be duplicated multiply,i.e., the number thereof may be considerable. On the other hand, anumber of long semi-floating potential regions F2 including a greatestlength but being double-contacted is limited by a lateral extension ofthe insulating intermediate region 145 along the Y direction next to theembedded transistor T_(s). The length of the long semi-floatingpotential regions F2 may exemplarily be in a range from 110 μm to 150 μmor be 130 μm and the length of the short semi-floating potential regionsF1 may exemplarily be in a range from 50 to 100 μm or exemplarily have avalue of roughly 75 μm.

However, since both the short semi-floating potential regions F1 and thelong semi-floating potential regions F2 are each contacted on two sides,an effective length of the semi-floating potential region F willcorrespond to half of the value indicated. Thus, the semi-floatingpotential regions F are uncritical with regard to simulations ofpossible error cases which, like described before, had the result thatsemi-floating potential regions of a length of less than 100 μmgenerally are uncritical. Metals may exemplarily be used as the materialfor the contact area M1 and for the other contact area M2 and the lead140.

Two further embodiments which only differ from the case illustrated inFIG. 2 a in that the straight opening region 120 b has been replaced byanother skewed opening region 120 b′ are illustrated in FIGS. 2 b and 2c, so that the boundary line 122 is also in a skewed relation to themesa stripes m_(i) and can intersect at least one, but also more than100 (exemplarily several 100 up to 1000) mesa stripes m_(i). In theembodiment of FIG. 2 b, the other skewed opening region 120 b′ has twoskewed boundary lines 122 a and 122 b which are connected by aconnection line 123 which is perpendicular to the mesa stripes m_(i). Inthe embodiment illustrated in FIG. 2 c, the connection line 123 is alsoin a skewed relation to the mesa stripes m_(i).

FIG. 3 illustrates a conventional design of the opening region 120 in acontact area M1. As can be seen, the opening region 120 is orientedalong the X direction and, compared to one embodiment, as is exemplarilyillustrated in FIGS. 2 a-2 c, does not include a skewed opening region120 a. FIG. 3 again illustrates an embedded transistor T_(s) which isconnected to the base line 130 via the lead 140 contacting the embeddedtransistor T_(s). In addition, the insulating intermediate region 145 isimplemented so as to electrically insulate the contact area M1 from theother contact area M2. In order to insulate the embedded transistorT_(s) and/or the body regions thereof correspondingly, it may benecessary (as described before) to form a thick oxide and/or the oxideregions D_(t) in the trench.

The result of designing the opening region 120 or, more precisely, theedge of the opening region 120 in parallel to the X direction and thusin parallel to the neighboring trenches t_(i) is that the correspondingsemi-floating potential regions F are considerably longer. There areshort semi-floating potential regions F1 which are contacted on bothsides by the contact area M1 and the length of which is uncritical,however it cannot be avoided with this kind of embedding that, inaddition to the short semi-floating potential regions F1, further longsemi-floating potential regions F2 result, the length of which in thisconventional design of the opening region 120 corresponds to theembedding depth. This means that the length of the long semi-floatingpotential regions F2 corresponds to the extension of the opening region120 along the X direction into the contact area M1.

Since the embedding depth generally is selected to be very large inorder to provide, as has been mentioned, optimum surroundings for theembedded transistor T_(s) (like for example a homogeneous potentialregion, equal temperature etc.), the long semi-floating potentialregions F2 are also very long. The long semi-floating potential regionsF2 may exemplarily include a length of 220 μm and the shortsemi-floating potential regions F1 may exemplarily include a length of140 μm. Since the short semi-floating potential regions F1 are contactedon both sides, however, the result is an effective length of roughly 70μm. Correspondingly, the short semi-floating potential regions F1 inthis conventional design are uncritical, however, the unavoidablyoccurring long semi-floating potential regions F2 include a length whichis clearly above the uncritical length. As has already been described,semi-floating potential regions F are critical starting from a length ofroughly 100 μm. Since the long semi-floating potential regions F2 areonly connected on one side (top), they are semi-floating in the bottompart (and exemplarily include body regions formed in mesa stripesm_(i)). Depending on the embedding depth of the current sensor, theresult here may be lengths of considerably more than 220 μm.Exemplarily, embeddings of roughly 1 mm are possible so that the lengthof the long semi-floating potential regions F2 would also be 1 mm.However, this is unacceptable, in particular when there are fasttransient processes (like for example in the form of ESD or ISO pulses).

FIG. 4 illustrates a more detailed description of the straight openingregion 120 b, the opening region 120 b being embedded in an integratedpower field-effect transistor. The power field-effect transistorincludes gate oxide trenches t₁, t₂, . . . , tn illustrated as thinlines in the X direction, which in the drawing is in the direction fromthe top to the bottom. The thick oxide trenches D_(t) serving forlimiting and insulating the sensor transistor T_(s) illustrated in thecenter of FIG. 4 are also in the X direction, but are, for improvedemphasizing purpose, indicated as thicker lines. The areas with skewedhatching are metal areas M1 and M2. The entire region illustrated,except for the portions with the thick oxide trenches D_(t) illustratedin thicker lines and the source implantation Simp discussed below,represents a body implantation (body region formed) and body contacts,which will become more obvious below referring to the sectional views ofFIGS. 5-7.

The layout illustrated in FIG. 4 keeps homogeneity interference low byusing (as far as possible, see farther below) a continuous gate oxideregion, i.e., the gate oxide trenches t₁, t₂, tn are continuous exceptfor the small-area regions of the thick oxide trenches D_(t). A CMP(chemical mechanical polishing) process which exemplarily follows laterin the process flow will see relatively homogenous conditions in thesurroundings of the sensor transistor T_(s), resulting in a more uniformlayer removal. The implantation of the body regions and the bodycontacts is, as far as possible, also formed over the entire area inorder to provide more uniform potential conditions.

Additionally, it can be seen in FIG. 4 that exemplarily an n⁺-dopedsource implant stripe Simp is above and below the embedded transistorand/or sensor transistor T_(s) in the X direction to suppress apotential parasitic MOS transistor on the surface (exemplarily p-channelon the surface of the n⁻-doped silicon between the two p-body regions ofthe power transistor and load transistor DMOS (double-diffused metaloxide semiconductor), respectively, and sensor transistor T_(s) and/orbetween the sensor transistor T_(s) and other p-regions on the chip).

The characteristics of the integrated MOS power switch discussed so far,like for example of the power field-effect transistor, as have beendiscussed before referring to the layout illustration in FIG. 1, willbecome more obvious using the schematic cross-sectional illustrationsillustrated in FIGS. 5 to 7 below.

FIG. 5 illustrates a cross-sectional view of FIG. 4 along theintersection line 2-2′, wherein only the left subregion is illustratedin an enlarged manner. Trenches t_(i) with the mesa stripes m_(i)therebetween are arranged in the substrate 110 (which is implementedhere as an n-epitaxial layer). The source regions 150 are formed alongthe mesa stripes m_(i) and the gate regions 160 are formed in thetrenches t_(i). The drain region 170 is formed on that side of thesubstrate 110 facing away from the trenches. The gate regions 160 areinsulated from the substrate 110 and from the body regions 220 by thegate oxide 180. The body regions 220 are formed between the drain region170 and the source regions 150 or the body through-contactings CB.

In FIG. 5, the source regions 150 which in this embodiment includen⁺-doped regions are formed only on the left side (exemplarily along themesa stripes m₁ and m₂) which corresponds to the region below thecontact area M1 along the cross section 2-2′. No source regions 150 areformed along the mesa stripes m₃ to m₇, but only bodythrough-contactings CB, wherein this region correspond to the regionbelow the insulating intermediate region 145. The bodythrough-contactings CB may exemplarily be implemented by p⁺-dopedregions. Thick oxide trenches D_(t) are formed on the right side of FIG.5 (along the mesa stripes m₈ and m₉), so that this region corresponds tothe region in the center of the cross section 2-2′ of FIG. 4. The thickoxide trenches D_(t) do not include body regions 220 or source regions150 so that the substrate 110 (the exemplarily n-epi layer) fills theentire mesa stripes m₈ and m₉. At the same time, the oxide layer 180within the trenches has greater a thickness at this position in order toprevent breakdown (as discussed before).

FIG. 6 illustrates a cross-sectional illustration in the Y directionalong the intersectional line 3-3′ of the layout of FIG. 4. Thecross-sectional view clearly illustrates that the trenches forming thefield of cells of the sensor transistor T_(s) structurally match thetrenches t1, t2, . . . of the field of cells of the load transistor DMOSin their geometry, regular sequence and setup on both sides (in the Ydirection) of the sensor transistor T_(s). The sensor transistor T_(s)is formed along other mesa stripes m_(s), the other mesa stripes m_(s)including other source regions 190, other gate regions and other bodyregions 230 and the sensor transistor T_(s) being separated from theload transistor (in the cross-sectional illustration of FIG. 6) by oxidelayers O. In the embodiment of FIG. 6, the p-doped body implantations220, 230 are also formed over the entire area along the sectionillustrated in the Y direction. Similar facts apply for the implantationof the body contact CB which fills the entire width of the mesa m_(i)between the trenches t_(i) below the oxide layers O (which represent anexample of the insulating intermediate region 145) and which outside theoxide layers O is in the center of the mesa m_(i) between two n⁺-dopedsource regions 150. As a precautionary measure, on the left- andright-hand sides outside the oxide layers O, a respective mesa m_(i) isfilled with the body 220 and the body contact CB over its entire width(an inactive mesa), the mesa m_(i) being contacted directly with thesource potential of the respective transistor (load DMOS and/or sensorDMOS), but which may also be omitted under certain circumstances. Likein FIG. 4, in FIG. 6, too, the remaining part of the DMOS loadtransistor is omitted in order to be able to illustrate details in theregion of the sensor transistor T_(s) better. The layout view in FIG. 4and the sectional view 3-3 of FIG. 6 illustrate the embodiment on thebasis of conventional metal design rules for power switches. However,this is not to be limiting, but the semiconductor device may also berealized using stricter design rules. In particular, the distancebetween active regions of the load DMOS and sensor DMOS may also bereduced in favor of improved embedding, since in this case a reducednumber of non-contacted mesas m_(i) will be necessary.

FIG. 7 is a sectional illustration along the intersection line 6-6′. Then⁺-doped source implant stripes Simp already discussed referring to FIG.4 can be seen below a respective oxide layer O above and below thesensor transistor T_(s). The p-doped body zone 220 and, above it, thep⁺-body contact CB and a region including an n⁺-doped source 150 and ap⁺-doped body contact CB can be seen in the region of the sensortransistor T_(s) and in the left illustrated portion of the load DMOS(in this view not visible in section). In addition, the portions presentin the integrated MOS power switch and the transition from and/orbetween gate-oxide trenches t_(i) and thick oxide trenches D_(t) arealso indicated in the bottom part of FIG. 7, i.e., below the n-epilayer.

The dopings illustrated in FIGS. 4 to 7 are only examples. Correspondingcomplementary dopings for the individual regions of the substrate 110 ora correspondingly stronger or weaker doping may be present in furtherembodiments.

FIG. 8 illustrates a schematic switching example of an MOS power switchequipped with a current sensor in high-side applications the MOStransistors of which are N-DMOS transistors. Among other things, acurrent sensor is usually integrated on the power switch chip in orderto realize self-protecting MOS power switches.

In one common embodiment, the current sensor is realized as a small DMOSsensor transistor T_(s) which provides a current proportional to theload current I_(L) flowing through the load DMOS transistor, provided itis wired to an identical voltage like the load DMOS. This DMOS sensortransistor T_(s) is, for example, smaller by a factor of 1,000 to100,000 than the load DMOS, and the current through it is a sensorcurrent which ideally is smaller by the geometrical ratio of the activeareas of the two transistors, namely the load DMOS and the sensortransistor T_(s), than the load current I_(L) through the load DMOS.This ratio will subsequently be referred to as the ideal ratio K_(G) ofthe currents, in contrast to the real ratio K of the currents.

When the integrated MOS power switch, as is illustrated in FIG. 8, isrealized in common-drain technology, both transistors, i.e., the loadDMOS and the sensor transistor T_(s), have the same drain potential andthe same gate potential. The source potential of the load DMOS istapped, as is exemplarily illustrated in FIG. 8, and the sourcepotential of the sensor transistor T_(s) is regulated to the samepotential. De facto, the real ratio K of the currents represents thequotient of the on resistances of the sensor transistor T_(s) and loadDMOS.

In a practical implementation, with small a load current, the load DMOSand sensor transistor T_(s) are operated at smaller a gate-sourcevoltage since, with high gate-source voltages, the voltage drop acrossthe load DMOS would be small and correspondingly the offset voltage ofthe differential amplifier U1 would influence the current measurementprecision more strongly. Under these conditions, the load DMOS andsensor transistor T_(s) are operated at a gate-source voltage which isclose to the starting voltage and thus operated at an operating pointwherein the channel resistance dominates the on resistance of the DMOStransistors. A difference in the starting voltage of the twotransistors, load DMOS and sensor transistor T_(s), in this operatingpoint results in great deviations of the real current ratio K from theideal geometrical ratio Kg.

Two operating modes have been realized in practice:

On the one hand, operation at high a gate-source voltage even with smallload currents. Good matching of the on resistance R_(ON) is importanthere. The current measurement precision here is limited by the offset ofthe downstream differential amplifier (see FIG. 8).

On the other hand, operation at low a gate-source voltage with smallload currents. Good matching of the starting voltages V_(ES) of the loadDMOS and the sensor transistor is important here since this matchinglimits the current measurement precision. With great load currents (andgreat a gate-source voltage), matching of the on resistance R_(ON) isagain important.

In order to achieve high precision of the current sensor under differentoperating conditions, the load DMOS and sensor transistor T_(s) have toexhibit good matching. Matching here means matching of thecharacteristic curves and equal starting voltages of the twotransistors. Furthermore, the sensor transistor should be embedded intothe active region of the load DMOS in the best manner possible in orderto achieve the most homogeneous current density possible in thesurroundings of the sensor transistor T_(s) and thus comparable voltagedrops, for example in the substrate 110 of the integrated MOS powerswitch.

Another embodiment for embedding the sensor transistor T_(s) isachieving (in the ideal case) equal temperatures in both transistors.This means that, when the load transistor DMOS heats up in the operatingstate, the sensor transistor T_(s) should heat up equally. Inconventional integrated MOS power switches, the distance from the loadDMOS to the sensor transistor is relatively great in order to takedesign rules in effect in conventional technologies (metal pitch, metaloverlap) into consideration. In order to realize embedding of the sensortransistor in the best way possible, the distances between the sensortransistor and the load DMOS transistor have to be minimized.

The embedding of the sensor transistor T_(s) is influenced considerablyby the design of the opening region 120. The design may be such that asufficiently great embedding depth d can be achieved with the smallestpossible loss in active area. This means that, on the one hand, theembedded sensor structure reaches a sufficiently great embedding depthd, however a corresponding lead should consume as little as area of thecontact area M1 as possible. Thus, the width of the elongate openingregion 120 should be as small as possible. However, it should be ensuredthat there is sufficient dimensioning so that low-resistance currentfeeding to the embedded semiconductor structure, like for example thesensor transistor T_(s), will be possible. The sufficiently greatembedding depth d should at the same time be accompanied by a limitedlength of the semi-floating potential regions F, exemplarily thesemi-floating potential regions F should not be longer than 100 μm (orat most 200 μm with two-side contacting).

Embodiments thus exemplarily relate to contacting a sensor structurewhich is embedded in a power field-effect transistor, wherein the leads(at least partly) are not designed to be perpendicular and/or parallelto the field of cells edges/chip edges/trench stripe direction, but arearranged in a skewed relation thereto. Thus, semi-floating potentialregions in the region of the leads are wired (contacted) to active cellson both sides. The active cells here correspond to the regions which arecontacted by the contact area M1. Sensor embedding here, as mentioned,takes place in a skewed manner, i.e., the position of the sensor centeris laterally offset to the position of the position where the leadenters into the field of cells region and/or the leads form one (orseveral) angles of greater than 10° and smaller than 90° with the fieldof cells/chip edges. The entering position of the leads here is thatposition on the base line 130 where the opening region 120 meets thebase line 130. The angles of the leads here exemplarily correlate tointeger multiples of the pitch distances of the field of cells in the Xand Y directions.

It is also to be mentioned that in other embodiments the embeddedcurrent sensor and/or embedded field-effect transistor may be replacedby all kinds or structures to be embedded which, as a consequence ofembedding, contain semi-floating regions. Embodiments also relate to acorresponding method of contacting a semiconductor device having theshape of the opening region 120 of the contact area M1 described before.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments illustrated and describedwithout departing from the scope of the present invention. Thisapplication is intended to cover any adaptations or variations of thespecific embodiments discussed herein. Therefore, it is intended thatthis invention be limited only by the claims and the equivalentsthereof.

1. A semiconductor device comprising: a substrate comprising a pluralityof neighboring trenches, one mesa stripe each being formed between twoneighboring trenches; and a contact area contacting the mesa stripes,the contact area surrounding an opening region in which no contact areais formed and which is shaped such that the contact area contacts thesame mesa stripes at two positions between which the opening region isarranged, and the opening region comprising a region of elongateextension which intersects the mesa stripes in a skewed or perpendicularmanner.
 2. The semiconductor device of claim 1, wherein the contact areais in an xy plane comprising X values and Y values and the neighboringtrenches extend along an X direction, an extension of the opening regionin the Y direction being at least 10% of an extension of the openingregion in the X direction.
 3. The semiconductor device of claim 2,wherein the extension in the X direction equals the extension in the Ydirection within a tolerance range of +/−20%.
 4. The semiconductordevice of claim 2, wherein the extension of the opening region in the Xdirection (Δx) and the extension of the opening region in the Ydirection (Δy) are defined such that the following applies: ½<Δy/Δx<3.5. The semiconductor device of claim 2, wherein the opening region isprovided with an edge by the contact area and the base line so that x=0applies for the base line, the base line forming an edge of the contactarea of maximum X values and the opening region comprising a perimeter Uand an area A, a first geometrical measure being defined by V₁=U/4 and asecond geometrical measure being defined by V₂=A/V₁, wherein thefollowing relation applies: V₁>V₂.
 6. The semiconductor device of claim1, wherein the opening region additionally comprises an edge region, theedge region abutting on the contact area and on the region of theelongate extension and being, with a boundary line, parallel to one ofthe mesa stripes and intersecting, with the boundary line, at most fivemesa stripes.
 7. The semiconductor device of claim 1, wherein theopening region additionally comprises an edge region, the edge regionabutting on the contact area and on the region of the elongate extensionand comprising skewed boundary lines and a connection line, theconnection line connecting the skewed boundary lines, and the connectionline and the skewed boundary lines intersecting a plurality of mesastripes, the plurality including a value between 1 and
 1000. 8. Thesemiconductor device of claim 1, wherein the region of the elongateextension is formed such that it intersects the mesa stripes in an angleα so that the following applies: tan α=n/m, n being an integer multipleof a pitch distance in a perpendicular direction to the neighboringtrenches and m being an integer multiple of a pitch distance in aparallel direction to the neighboring trenches, the pitch distance inthe perpendicular direction corresponding to a distance of two of theneighboring trenches and the pitch distance in the parallel directioncorresponding to a distance of two contacts spaced in a trench directionto one of the mesa stripes.
 9. The semiconductor device of claim 1,wherein the contact area ends in a corner region along a base line andpart of the opening region is arranged in the corner region.
 10. Thesemiconductor device of claim 1, wherein another contact area whichcontacts the mesa stripes or other mesa stripes is formed within theopening region and the other contact area is electrically insulated fromthe contact area.
 11. The semiconductor device of claim 10, wherein theopening region comprises an embedded semiconductor structure and theembedded semiconductor structure is contacted electrically by the othercontact area, and at least one lead and wherein the lead comprises anelectrical contact to the embedded semiconductor structure and iscoupleable electrically.
 12. The semiconductor device of claim 11,wherein the embedded semiconductor structure comprises a field-effecttransistor, wherein the other contact area forms another sourceterminal, and wherein doped regions along the mesa stripes or the othermesa stripes form another source region so that the other contact areacontacts the other source region and another insulation region is formedbetween the other source region and the source region, and wherein adrain electrode is formed on a side of the substrate facing away fromthe other contact area, and wherein another gate region is formed withinthe neighboring trenches or within other trenches between the other mesastripes, the other gate region comprising another insulation to thesubstrate and the other contact area.
 13. The semiconductor device ofclaim 1, wherein the contact area forms a source terminal for a powerfield-effect transistor and the power field-effect transistor comprisesa source region, a gate region and a drain region, wherein the sourceregion is formed by doped regions along the mesa stripes and is inelectrical contact to the contact area, and wherein the drain region isformed on a side of the substrate facing away from the contact area, andwherein the gate region is formed within the neighboring trenches, thegate region comprising an electrical insulation to the substrate.
 14. Asemiconductor sensor structure including a power field-effect transistorcomprising a source region, a gate region and a drain region, andanother field-effect transistor comprising another source region andanother gate region, comprising: a substrate comprising a plurality ofneighboring trenches, one mesa stripe each being formed between twoneighboring trenches, doped regions of a mesa stripe forming the sourceregion and other doped regions of the mesa stripe or another mesa stripeforming the other source region; a contact area contacting the sourceregion, the contact area surrounding an opening region in which nocontact area is formed and which is shaped such that the contact areacontacts the same mesa stripes at two positions between which theopening region is arranged, and the opening region comprising a regionof elongate extension which intersects the mesa stripes in a skewed orperpendicular manner; and another contact area extending in the openingregion, comprising an electrical contact to the other source region andbeing electrically insulated from the contact area, and wherein thedrain region is formed on that side of the substrate facing away fromthe contact area and includes a drain terminal for the powerfield-effect transistor and the other field-effect transistor, andwherein the gate region is formed within trenches between the mesastripes and the other gate region is formed within the trenches orwithin other trenches between the other mesa stripes and comprisesanother electrical insulation to the substrate.
 15. The semiconductorsensor structure of claim 16, wherein the mesa stripes comprise a bodyregion between the source region and the drain region, and wherein theother mesa stripes comprise another body region between the other sourceregion and the drain region, the body region and the other body regioncomprising a doping of the semiconductor substrate which iscomplementary compared to the drain region.
 16. The semiconductor sensorstructure of claim 15, wherein the other field-effect transistor is acurrent sensor for the power field-effect transistor (DMOS), the otherfield-effect transistor and the power field-effect transistor (DMOS)being coupleable to an equal drain potential and to an equal gatepotential.
 17. The semiconductor sensor structure of claim 15, whereinan insulation region is formed between the body region and the otherbody region and the body region comprises an electrical contacting tothe contact area and the other body region comprises another electricalcontacting to the other contact area.
 18. An apparatus for manufacturinga device including a power field-effect transistor in a substratecomprising a plurality of neighboring trenches, one mesa stripe eachwhich extends to a surface of the substrate being formed betweenneighboring trenches, comprising: first means for providing a firstcontact, the first means being formed on a side of the substrate facingaway from the surface; second means for providing a second contact, thesecond means being implemented as a contact area which contacts the mesastripes, the second means surrounding an opening region in which thesecond means is not formed and which is formed such that the secondmeans contacts the same mesa stripes at least two positions betweenwhich the opening region is arranged; third means for providing a thirdcontact, the third means being implemented as another contact area whichcontacts the mesa stripes or other mesa stripes, the third means beingformed within the opening region and being electrically insulated fromthe second means; fourth means for providing a control contact, thefourth means being formed at least partly in the neighboring trenchesand comprising an electrical insulation to the substrate; and whereinthe opening region comprises a region of elongate extension whichintersects the mesa stripes in a skewed or perpendicular manner, andwherein the power field-effect transistor is electrically coupleable bythe first and second contacts and controllable by the control contact,the device being electrically coupleable by the first and thirdcontacts.
 19. A method of manufacturing a semiconductor device,comprising: providing a substrate comprising a plurality of neighboringtrenches, one mesa stripe each being formed between two neighboringtrenches; forming a contact area contacting the mesa stripes, thecontact area surrounding an opening region in which no contact area isformed and which is formed such that the contact area contacts the samemesa stripes at two positions between which the opening region isarranged, and the opening region comprising a region of elongateextension which intersects the mesa stripes in a skewed or perpendicularmanner, wherein the semiconductor device is contacted electrically bythe contact area.
 20. The method of claim 19, wherein forming thecontact area is performed such that an extension of the opening regionin the X direction (Δx) equals an extension of the opening region in theY direction (Δy) within a tolerance range of +/−20%.
 21. The method ofclaim 19, wherein forming the contact area is performed such that theopening region defines the extension of the opening region in the Xdirection (Δx) and the extension of the opening region in the Ydirection (Δy) such that the followings applies: ½<Δy/Δx<3.
 22. Themethod of claim 19, further including forming another contact areawithin the opening region so that the other contact area is electricallyinsulated from the contact area.
 23. The method of claim 22, wherein theopening region comprises an embedded semiconductor structure, andwherein forming another contact area is performed such that the embeddedsemiconductor structure is contacted electrically by the other contactarea.
 24. The method of claim 23, wherein the embedded semiconductorstructure comprises a sensor field-effect transistor, and whereinforming the contact area and forming the other contact area areperformed such that a ratio of the areas of the contact area and theother contact area results in a predetermined ratio such that a currentthrough the semiconductor device and another current through the sensorfield-effect transistor are in a predetermined ratio to each other. 25.A method of manufacturing a device and a power field-effect transistorin a substrate comprising a plurality of neighboring trenches, one mesastripe each which extends to a surface of the substrate being formedbetween neighboring trenches, comprising: providing first means for afirst contact, the first means being formed on a side of the substratefacing away from the surface; providing second means for a secondcontact, the second means being implemented as a contact area whichcontacts the mesa stripes, the second means surrounding an openingregion in which the second means is not formed and which is formed suchthat the second means contacts the same mesa stripes at least at twopositions between which the opening region is arranged; providing thirdmeans for a third contact, the third means being implemented as anothercontact area which contacts the mesa stripes or other mesa stripes, thethird means being formed within the opening region and beingelectrically insulated from the second means; providing fourth means fora control contact, the fourth means being formed at least partly in theneighboring trenches and comprising an electrical insulation to thesubstrate; and wherein the opening region comprises a region of elongateextension which intersects the mesa stripes in a skewed or perpendicularmanner, and wherein the power field-effect transistor is electricallycoupleable by the first and second contacts and controllable by thecontrol contact, the device being electrically coupleable by the firstand third contacts.